The present invention relates to a dynamic random access memory (DRAM) device and, more particularly, to a DRAM device capable of performing a partial refresh operation and a method thereof.
In general, a DRAM device consists of memory cells each of which consists of a capacitor and a transistor. Data is stored in a capacitor of each memory cell. Data stored in a capacitor is lost due to a decrease in charges in the capacitor according to leakage over time. Accordingly, the DRAM device has a disadvantage that data stored in the capacitor can be lost as time elapses. In order to solve such a problem, the DRAM device necessitates a refresh operation in which data in memory cells is retained through periodic amplification.
In the event that a system operates in a normal mode, a DRAM device may store or read data in or from memory cells in response to a read/write access command. After such accesses, a DRAM device may perform a refresh operation. In general, a refresh operation may be carried out with respect to all memory cells regardless of whether data is stored or not. Since a refresh operation is carried out with respect to memory cells that do not store data to be retained, unnecessary power may be consumed.